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Summary Multiple‐stage complementary metal‐oxide‐semiconductor （CMOS） operational amplifiers （Op Amps） have been extensively studied in the literature; often, each new design reports several performance advancements over the existing ones. However, the design space boundaries of those new proposals were rarely explored. Predicting the design space boundary of a new circuit topology is usually challenging due to the dependency on many aspects of technical consideration regarding the process technology, sizing priority adopted in practice, and balancing of performance metrics on power, area, noise immunity, and so on. Knowing the design space boundary could be beneficial to a fair appraisal of new designs. In this paper, we propose a gm/ID‐based method for the design space exploration of multistage Op Amps. By introducing a sampling technique while taking advantage of the device grouping property with gm/ID, it is possible to explore the circuit performance boundary by combining approximate symbolic modeling and gm/ID table lookup. Due to the introduction of a fast performance evaluation method, a large ensemble of circuit sizing samples can be evaluated in parallel, by which an efficient data mining procedure could be incorporated to deduce the circuit samples that can achieve extremal performance at Pareto boundaries. The fidelity of this proposal has been validated via simulation program with integrated circuit emphasis （SPICE） . The sampling method is also compared with a multi‐objective genetic algorithm to show the superiority in capturing Pareto boundaries.
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