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Queue modeling is an important step in Networks-on-Chip (NoC) design to understand and estimate the system behavior at early design phases. Choosing queue parameters, such as queue size, maximum packet arrival rate, packet service rate, directly impacts the performance and silicon area of the overall NoC-based design. In this paper, we propose a new 2D M/D/1/B queuing model for NoC routers. Using our model, we prove that packet service rate impacts throughput significantly. On the other hand, changing the queue size, within acceptable ranges for NoC applications, does not have a noticeable effect on the throughput. Through a case study implementation on FPGA, we explain how this model could be used in different applications to obtain design parameters at higher levels of abstraction. Synthesis and performance analysis are performed to validate the proposed model.
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