[期刊论文]

出版年：2018

Binary Decision Diagrams (BDDs) are very useful structures to represent Boolean function in VLSI synthesis. Time taken to build a BDD and obtaining its size plays a major role in the time of complexity of VLSI synthesis. This time complexity increases drastically as the number of input variables increases. Various models to estimate the size of the BDD, without actually building it already exists. These models claim to support both simplified and un-simplified Boolean functions. The models were developed under the justification that time to estimate will be far less compared to the time taken to actually build the BDD. There are two drawbacks with the existing model. First drawback is that, the current model just follows a random curve fit without any substantial mathematical support. Second drawback is the existing model is based on experimental results which used only less than ten variables.  Since current practical functions may use hundreds of variables, there is no guarantee that the model is accurate enough. Given the two drawbacks, it becomes necessary to test the existing model for more complex circuits with hundreds of variables. In this paper the existing models were tested with standard benchmark circuits. Results were compared with actual BDD sizes of the benchmarks and the estimated sizes from the parameters of the benchmarks. Comparison of the results proved that existing models give poor results for the circuits with more than ten variables and existing models become inapplicable to most of the current practical functions that uses more than hundreds of variables.  

Binary Decision Diagrams, Modeling, Invalidation.