[期刊论文]

出版年：2008

A hardware architecture for naive Bayes inference engine to classify e-mail contents for spam control is proposed. The inference engine utilises the logarithmic number system (LNS) to simplify naive Bayes computations. For high throughput LNS recoding, a non-iterative binary LNS recoding hardware architecture that uses look-up table approach is proposed. A noise model for the inference engine was developed and the noise bounds were analysed to determine the inference accuracy. The inference engine design is synthesised targeting the Altera Stratix field programmable gate array (FPGA) device. From the synthesis results, the binary LNS naive Bayes inference engine was found to have the capability to classify more than 117 million features per second, given a stream of a priori and likelihood probabilities as input with small computation noise. The synthesised inference engine was functionally verified against a MATLAB implementation.

binary LNS-based naive Bayes inference engine; spam control; noise analysis; FPGA implementation; e-mail contents classification; logarithmic number system; noniterative binary LNS recoding hardware architecture; look-up table; noise model; Altera Stratix field programmable gate array; FPGA device