[期刊论文]

出版年：2013

One of the challenging problems in networks-on-chip (NoC) design is optimising the architectural structure of the on-chip network in order to maximise the network performance while minimising the corresponding costs. In this study, a methodology for multi-objective optimisation of NoC standard architectures using Genetic Algorithms is presented. The methodology considers two cost metrics, power and area, and two performance metrics, delay and reliability. Our methodology combines the best selection of NoC standard topology, the optimum mapping of application cores onto that topology, and the best routing of application traffic traces over the generated network. The methodology is evaluated by applying it to different NoC benchmark applications as case studies. Results show that the architectures generated by our methodology outperform those of other standard architecture customisation techniques with respect to four metrics: power, area, delay and reliability, and their combination.

genetic algorithms; integrated circuit design; integrated circuit reliability; network routing; network-on-chip; NoC standard architectures; application traffic; architectural structure; area cost metric; cost minimization; delay performance metric; genetic algorithms; multiobjective optimisation; network performance maximization; networks-on-chip design; power cost metric; reliability performance metric; unified multiobjective architecture customisation; unified multiobjective mapping customisation;